The present invention relates to a low power operational amplifier circuit with slew rate enhancement and more particularly to a CMOS operational amplifier circuit with bipolar current enhancement transistors for supplying extra current to the CMOS differential input stage when the operational amplifier is under large signal conditions.
Operational amplifier circuits receive a differential signal at a differential input and produce a single ended output signal as an amplified representation of the input signal. The typical operational amplifier circuit comprises a differential input stage for receiving and amplifying the input signal followed by a single ended amplifier for receiving the amplified signal from the differential amplifier and converting it into a single ended output. Usually, the single ended amplifier includes a compensation network for stabilizing the operational amplifier.
The differential input for the operational amplifier comprises a plus input and a minus input, wherein the differential signal corresponds to the voltage between the plus and minus inputs. With reference to a prior art CMOS design as shown in FIG. 1, the gate of a P-channel transistor 2 corresponds to the minus input while the gate of a P-channel transistor 4 corresponds to the plus input. The two P-channel FETs 2 and 4 are joined at their sources at a current source node 15 which receives a bias current I.sub.1 from a current source 16. The drain of transistor 2 is coupled to the drain and gate of an N-channel transistor 9 while the drain of transistor 4 is coupled first, to the drain of an N-channel transistor 10, second, to the gate of an output N-channel transistor 11 and third, to the capacitor C of a compensation network. The gate of transistor 10 is coupled to the gate of transistor 9 and the sources of both transistors 9 and 10 are returned to lower supply voltage V.sub.ss. Transistors 9 and 10 act as a current mirror for reproducing at the drain of transistor 10 a current corresponding to the current flowing through transistor 9.
When the differential input voltage is zero between the plus and minus inputs, current I.sub.1 splits equally between each leg of the differential amplifier. The leg of the differential amplifier corresponding to transistors 4 and 10 receives one-half of the current I.sub.1, and the other leg of the differential amplifier corresponding to transistors 2 and 9 receives the other half of the current. With this condition, transistor 10 passes a current identical to that in transistor 9, I.sub.1 /2, and no current flows to or from compensation capacitor C for discharging or charging the capacitor.
When a voltage is received between the differential inputs of the operational amplifier, the differential input stage amplifies the received input voltage and produces an interstage signal sent to the gate of transistor 11. It may be shown for small signal conditions (wherein the operational amplifier operates in the linear region without any transistors saturating or turning off) that the gain of the differential input amplifier is equal to: EQU A.sub.v =g.sub.m4 /(g.sub.o10 g.sub.o4)
where A.sub.v is the small signal gain of the differential amplifier, g.sub.m4 the transconductance of transistor 4, and g.sub.o4 and g.sub.o10 the output admittances of transistors 4 and 10 respectively.
Transistor 11 receives the amplified output signal from the differential input stage and amplifies the signal according to a similar relationship such that the output voltage V.sub.out is equal to: ##EQU1## where g.sub.m11 is the transconductance of transistor 11, g.sub.o11 the output admittance of transistor 11, g.sub.o17 the output admittance of current source 17 supplying transistor 11 and V.sub.gs11 the voltage across the gate and source of transistor 11. Note that the effects of "pole" compensation capacitor C and "zero" compensation resistor R.sub.z of the compensation network have been ignored so far.
An ideal operational amplifier provides infinite gain over the entire frequency spectrum. However, real world devices experience frequency limitations and feedback problems such that an operational amplifier without proper compensation runs the risk of oscillating or producing undesirable ringing transients. Therefore, to avoid excessive ringing or oscillation, compensation network C and R.sub.Z is provided in the series feedback path between the drain and gate of output transistor 11. With respect to the frequency domain, capacitor C provides a dominate "pole" for the transfer function of the operational amplifier and resistor R.sub.z optimizes the operational amplifier's frequency response by providing a properly positioned "zero" for the transfer function of the operational amplifier.
It may be shown that the output voltage produced by the operational amplifier in response to an abrupt voltage step at the differential input has a limited rise time. The rise time of the output voltage is limited by the finite bias current I.sub.1 available for the differential input stage (at current source node 15) and compensation capacitor C. For FIG. 1, this maximum slew rate SR.sub.max for the output voltage is: ##EQU2##
Improving the slew rate performance of the compensated operational amplifier requires either increasing current I.sub.1 or decreasing the value of compensation capacitor C. Increasing current I.sub.1 increases the power the operational amplifier dissipates. Decreasing the capacitor value C may reintroduce the ringing troubles and/or oscillation problems. Thus, the standard FET operational amplifier suffers a power/stability/slew rate compromise.
FIG. 2 shows a prior art bipolar operational amplifier circuit with circuitry for improving the slew rate performance of the bipolar operational amplifier. The basic operational amplifier configuration is provided with bipolar transistors 2', 4', 9', 10', 11', current I and compensation capacitor C'. Under small signal conditions, the bipolar operational amplifier circuit receives a differential input signal between the bases of transistors 2' and 4'. The differential amplifier including transistors 2' and 4' amplifies the differential input signal and produces an interstage output signal at the collector of transistor 10' which is sent to output transistor 11' for supplying output voltage V.sub.OUT as an amplified representation of the differential input signal.
The basic operational amplifier topology suffers a slew rate limitation according to the original bias current I=I.sub.o and compensation capacitor C. However, the circuit of FIG. 2 includes slew rate enhancement circuitry comprising transistors 1', 3', 5, 6, 7 and 8, resistors 20, 21 and 22, as well as current sources 18' and 19' for enhancing the slew rate performance. If a sudden voltage amplitude step is received at the differential input, i.e., a large signal condition, then the slew rate enhancement circuitry operates to increase current I flowing to the differential pair 2' and 4' so as to enhance the current available for either charging or discharging, depending upon the polarity of the amplitude step, compensation capacitor C.
For example, assume that a positive large signal voltage step is received between the plus and minus inputs. The base of transistor 3' receives an increased voltage which increases, via voltage shifter 6, the voltage at the base of transistor 8, in turn causing transistor 8 to flow a larger current than before for providing an enhanced bias current I=I.sup.+ with I.sup.+ =I.sub.o +.DELTA.I wherein the additional current supplied .DELTA.I is a function of the large signal amplitude. Without the slew rate enhancement circuitry, only the original bias current I.sub.o would be available for the differential amplifier, but with the slew rate enhancement circuitry, the current I available for the differential amplifier increases according to the magnitude of the large signal received at the differential input. When the large signal voltage is great enough, transistor 4' turns off completely and all of the current supplied to the differential pair flows through transistor 2' and through transistor 9' of the current mirror. The enhanced current I.sup.+ flowing through transistor 9' provides a given voltage drop between the base and emitter of transistor 9' and consequently between the base and emitter of transistor 10' of the current mirror for enabling a substantially identical enhanced current I.sup.+ through transistor 10'. With transistor 4' turned off, the enhanced current I.sup.+ passing through transistor 10' is drawn from capacitor C' and discharges capacitor C' until the required output voltage is produced or until the output transistor of the current source 17' saturates. As capacitor C' integrates the enhanced current I.sup.+, charge accumulates across the capacitor and the output voltage ramps up with an enhanced slew rate limited by C' and the enhanced current I.sup.+. Note that without the slew rate enhancement circuitry, the slew rate was limited according to the original small signal bias current I.sub.o supplied to the differential amplifier.
When the voltage polarity of the large signal unit step applied to the differential input is opposite that described above, the circuit operates a little differently. The base of transistor 1' receives an increased voltage potential and the base of transistor 3' a decreased voltage potential. The base of transistor 7 receives via voltage shifter 5 the higher voltage for enabling transistor 7 to pass an enhanced current I.sup.+ greater than the original small signal bias current I.sub.o. On the other side of the differential amplifier, the lower voltage potential is coupled via voltage shifter 6 to the base of transistor 8. If the magnitude of the differential input voltage is large enough, transistor 8 turns off completely and likewise transistor 2'. Under such conditions, the enhanced current I.sup.+ supplied to the differential amplifier flows through transistor 4' toward the collector node of transistor 10'. With transistor 2' turned off, transistor 9' of the current mirror does not conduct any current and transistor 10' is disabled such that all the current through transistor 4' flows to compensation capacitor C' until the required output voltage is obtained or until transistor 11' saturates. Compensation capacitor C' integrates the enhanced current for ramping the output voltage downward with a slew rate proportional to the enhanced current I.sup.+ divided by capacitor C'. In this manner, the bipolar operational amplifier of FIG. 2 with slew rate enhancement provides typical small signal amplification when the amplitude of the differential input signal is less than a given large signal threshold, and when the amplitude of the differential input signal is greater than the given large signal threshold, the slew rate enhancement circuitry supplies additional current for enhancing slew rate performance.
However, there is a penalty in that the bipolar operational amplifier with the slew rate enhancement circuitry consumes extra power. Under a condition of zero volts applied to the differential input, slew rate enhancement transistors 7 and 8 establish a bias state for the differential amplifier according to currents I.sub.b ' of the current sources 18' and 19' and the resistance ratio of resistors 20 and 21 with respect to resistor 22. For FIG. 2, it may be shown for such a condition that the current I will equal twice I.sub.b ', (assuming the transistors have similar geometries and doping profiles) and that therefore the bipolar differential amplifier stage with the slew rate enhanced circuitry dissipates twice the power of the standard differential amplifier.
What is desired, therefore, is a slew rate enhanced operational amplifier circuit which dissipates low power under small signal conditions without sacrificing stability.